1 block diagram features ? ? f max < 1.5ghz ? ? 10 pairs of diferential lvpecl/ ecl outputs ? ? low additive jitter, < 0.03ps (typ) ? ? selectable diferential input pairs with single ended input option ? ? input clk accepts: lvpecl, lvds, cml, sstl input level ? ? output skew: 55ps (max) ? ? operating temperature: -40 o c to 85 o c ? ? ecl mode operating voltage range v dd / v ddo = 0v, v ee = -3.6v to -2.375v ? ? power supply: 3.3v 10% or 2.5v 5% ? ? packaging (pb-free & green), 32-pin tqfp available description te PI6C4911510-05 is a high-performance low-skew 1-to-10 lvpe - cl/ ecl fanout bufer. te PI6C4911510-05 features two selectable diferential clock inputs and translates to ten lvpecl/ ecl outputs. te clk inputs accept lvpecl, lvds, cml and sstl signals. PI6C4911510-05 is ideal for clock distribution applications such as providing fanout for low noise pericom oscillators. pin configuration clk0 nclk0 clk_sel q0+ q0- 0 1 q1+ q1- q2+ q2- q3+ q3- q4+ q4- q5+ q5- q6+ q6- q7+ q7- q8+ q8- q9+ q9- clk1 nclk1 d le q sync_oe 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 vdd clk_sel clk0 nclk0 sync_oe clk1 nclk1 vee vddo q9- q9+ q8- q8+ q7- q7+ vddo q3+ q3- q4+ q4- q5+ q5- q6+ q6- vddo q0+ q0- q1+ q1- q2+ q2- vddo 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer with sync oe p i 6 c 4911510 - 0 5 PI6C4911510-05 rev c 10/09/2013 13-0151
2 clk_sel input function table inputs outputs 0 clk0 1 clk1 pin description pin # name ty pe description 1 v dd power core power supply 2 clk_sel input clock select input. when high, selects clk1 input. when low, selects clk0 input. lvcmos/lvttl level with 50k? pull down. 3 clk0 input diferential clock input with pull-down 4 nclk0 input inverting diferential clock input. defaults to v dd /2 if lef foating. 5 sync_oe input synchronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 6 clk1 input diferential clock input with pull-down 7 nclk1 input inverting diferential clock input. defaults to v dd /2 if lef foating. 8 v ee power connect to negative power supply 9, 16, 25, 32 v ddo power output power pin 11, 10 q9+, q9- output diferential output pair, lvpecl interface level. 13,12 q8+, q8- output diferential output pair, lvpecl interface level. 15,14 q7+, q7- output diferential output pair, lvpecl interface level. 18,17 q6+, q6- output diferential output pair, lvpecl interface level. 20,19 q5+, q5- output diferential output pair, lvpecl interface level. 22,21 q4+, q4- output diferential output pair, lvpecl interface level. 24, 23 q3+, q3- output diferential output pair, lvpecl interface level. 27, 26 q2+, q2- output diferential output pair, lvpecl interface level. 29,28 q1+, q1- output diferential output pair, lvpecl interface level. 31,30 q0+, q0- output diferential output pair, lvpecl interface level. PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
3 sync_oe input function table input outputs sync_oe q[0:9]+ q[0:9]- 0 disabled; low disabled; high 1 enabled enabled inputs outputs input to output mode polarity clk0 or clk1 nclk0 or nclk1 q[0:9]+ q[0:9]- 0 1 low high diferential to diferential non inverting 1 0 high low diferential to diferential non inverting 0 biased low high single ended to diferential non inverting 1 biased high low single endded to diferential non inverting biased 0 high low single endded to diferential inverting biased 1 low high single endded to diferential inverting clock input function table enabled disabled clk[0:1] nclk[0:1] sync_oe q[0:9]- q[0:9]+ notes: 1. exact enable/ disable time shown above only valid for frequencies <200mhz. PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
4 absolute maximum ratings (1) symbol parameter conditions min ty p max units v dd supply voltage referenced to gnd 4.6 v v in input voltage referenced to gnd -0.5 v dd +0.5v v i out surge current 100 ma t stg storage temperature -55 150 o c note: 1. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these ratings are stress specifca - tions only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may af fect product reliability. operating conditions symbol parameter conditions min ty p max units v dd core power supply voltage 3.0 3.6 v 2.375 2.625 v ddo output power supply voltage 3.0 3.6 v 2.375 2.625 t a ambient temperature -40 85 o c i dd core power supply current 90 ma i ddo output power supply current all lvpecl outputs unloaded 110 lvcmos/lvttl dc characteristics (ta = -40 o c to +85 o c, vdd = 3.3v 10%, vddo = 2.5v 5% to 3.3v 10 % ) symbol parameter conditions min ty p max units v ih input high voltage clk_sel, sync_oe 1.7 v dd +0.3 v v il input low voltage clk_sel, sync_oe -0.3 i ih input high current clk_sel, sync_oe v in = v dd = 3.6v 150 a i il input low current clk_sel, sync_oe v in = 0v, v dd = 3.6v -150 a PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
5 ac characteristics (t a = -40 o c to +85 o c, v dd = 3.3v 10%, v ddo = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units f max output frequency 1500 mhz t pd propagation delay (1) 1200 2100 ps tsk output-to-output skew (2) 40 55 ps tsk(p-p) part-to-part skew (3) 250 ps t r /t f output rise/fall time 20% - 80% 150 ps t odc output duty cycle f 650 mhz 48 52 % v pp output swing lvpecl outputs, f 650 mhz 400 mv t j bufer additive jitter rms 156.25mhz with 12khz to 20mhz integration range 0.03 ps notes: 1. measured from the diferential input to the diferential output crossing point 2. defned as skew between outputs at the same supply voltage and with equal loads. measured at the output diferential crossing point 3. tis parameter is guaranteed by design lvpecl dc characteristics ( t a = -40 o c to +85 o c, v dd = 3.3v 10%, v ddo = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units i ih input high current clk0, clk1 v in = v dd = 3.6v 150 a nclk0, nclk1 v in = v dd = 3.6v 150 a i il input low cur - rent clk0, clk1 v dd = 3.6v, v in = 0v -150 a nclk0, nclk1 v dd = 3.6v, v in = 0v -150 a v pp peak-to-peak voltage 0.4 0.8 v v cmr common mode input voltage (1) v ee +0.5 v dd - 0.85 v v oh output high voltage (2) v ddo = 2.5v or 3.3v v ddo -1.4 v ddo -0.9 v v ol output low voltage (2) v ddo = 2.5v or 3.3v v ddo -2.0 v ddo -1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v r input pullup/pulldown resistance 50 k? notes: 1. for single-ended applications, the maximum input voltage for clk and /clk is v dd +0.3v 2. outputs terminated with 50 to v dd -2.0v PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
6 configuration test load board termination for lvpecl outputs 100 z = 5 0 o z = 5 0 o 150 150 lvpec l buff er v ddqx l = 0 ~ 10 in. PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
7 pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com ordering information (1,2,3) ordering code package code package description PI6C4911510-05faie fa pb-free & green, 32-pin tqfp notes: 1. t hermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb -free & green 3. x s uffx = tape/reel packaging mechanical: 32-pin tqfp (fa) 1 seating plane 0.80 bsc .032 0.30 0.45 .012 .018 1.20 .047 0.95 1.05 .037 .041 x.xx x.xx denotes dimensions in millimeters 9.00 bsc .276 square 7.00 bsc .354 square gauge plane 1.00 ref .039 0.45 0.75 .018 .030 0.09 0.20 .004 .008 0 7 0.25 mm max. 0.10 .004 0.05 0.15 .002 .006 description: 32-pin, thin quad flat package, tqfp package code: fa document control no. pd - 1814 revision: c date: 03/09/05 pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com notes: 1. controlling dimensions in millimeters 2. ref.: jedec ms-026d/aba 3. package outline exclusive of mold flash and metal burr PI6C4911510-05 rev c 10/09/2013 PI6C4911510-05 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ sync oe 13-0151
|
